-- ============================================================================
-- 74XX00 Quad 2-Input NAND Gates
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX00 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
a4 : in std_logic;
b4 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX00 is
begin
o1 <= '0' after tphl when (a1 and b1) = '1' else
'1' after tplh;
o2 <= '0' after tphl when (a2 and b2) = '1' else
'1' after tplh;
o3 <= '0' after tphl when (a3 and b3) = '1' else
'1' after tplh;
o4 <= '0' after tphl when (a4 and b4) = '1' else
'1' after tplh;
end architecture;
Sunday, September 28, 2008
VHDL PROGRAM OF A74XX00_vhd
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VHDL PROGRAM OF A74XX00-Test_vhd
-- ============================================================================
-- 74XX00 Quad 2-Input NAND Gates (Test Bench)
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX00_TestBench is
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A74XX00_TestBench is
component A74XX00 is
generic (
tplh : time;
tphl : time);
port (
a1 : in std_logic;
b1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
a4 : in std_logic;
b4 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic);
end component;
signal ab : std_logic_vector (1 to 2);
signal wx : std_logic_vector (1 to 2);
signal o : std_logic_vector (1 to 4);
begin
-- Normal test pattern
ab <= "UU",
"00" after 10 ns,
"01" after 20 ns,
"10" after 30 ns,
"11" after 40 ns,
"LL" after 50 ns,
"LH" after 60 ns,
"HL" after 70 ns,
"HH" after 80 ns;
-- Inverted test pattern
wx <= "UU",
"11" after 10 ns,
"10" after 20 ns,
"01" after 30 ns,
"00" after 40 ns,
"HH" after 50 ns,
"HL" after 60 ns,
"LH" after 70 ns,
"LL" after 80 ns;
-- Connect the testbench to the component
nand2: A74XX00
generic map (
tplh => 5 ns, tphl => 7 ns)
port map (
ab(1), ab(2),
ab(1), wx(2),
wx(1), ab(2),
wx(1), wx(2),
o(1), o(2), o(3), o(4));
end architecture;
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VHDL PROGRAM OF A74XX02_vhd
-- ============================================================================
-- 74XX02 Quad 2-Input NOR Gates
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX02 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
a4 : in std_logic;
b4 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX02 is
begin
o1 <= '0' after tphl when (a1 or b1) = '1' else
'1' after tplh;
o2 <= '0' after tphl when (a2 or b2) = '1' else
'1' after tplh;
o3 <= '0' after tphl when (a3 or b3) = '1' else
'1' after tplh;
o4 <= '0' after tphl when (a4 or b4) = '1' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX02-Test_vhd
-- ============================================================================
-- 74XX02 Quad 2-Input NOR Gates (Test Bench)
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX02_TestBench is
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A74XX02_TestBench is
component A74XX02 is
generic (
tplh : time;
tphl : time);
port (
a1 : in std_logic;
b1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
a4 : in std_logic;
b4 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic);
end component;
signal ab : std_logic_vector (1 to 2);
signal wx : std_logic_vector (1 to 2);
signal o : std_logic_vector (1 to 4);
begin
-- Normal test pattern
ab <= "UU",
"00" after 10 ns,
"01" after 20 ns,
"10" after 30 ns,
"11" after 40 ns,
"LL" after 50 ns,
"LH" after 60 ns,
"HL" after 70 ns,
"HH" after 80 ns;
-- Inverted test pattern
wx <= "UU",
"11" after 10 ns,
"10" after 20 ns,
"01" after 30 ns,
"00" after 40 ns,
"HH" after 50 ns,
"HL" after 60 ns,
"LH" after 70 ns,
"LL" after 80 ns;
-- Connect the testbench to the component
nand2: A74XX02
generic map (
tplh => 5 ns, tphl => 7 ns)
port map (
ab(1), ab(2),
ab(1), wx(2),
wx(1), ab(2),
wx(1), wx(2),
o(1), o(2), o(3), o(4));
end architecture;
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VHDL PROGRAM OF A74XX04_vhd
-- ============================================================================
-- 74XX04 Hex Inverter
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX04 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
i4 : in std_logic;
i5 : in std_logic;
i6 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic;
o5 : out std_logic;
o6 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX04 is
begin
o1 <= '0' after tphl when not to_bit(i1) = '0' else
'1' after tplh;
o2 <= '0' after tphl when not to_bit(i2) = '0' else
'1' after tplh;
o3 <= '0' after tphl when not to_bit(i3) = '0' else
'1' after tplh;
o4 <= '0' after tphl when not to_bit(i4) = '0' else
'1' after tplh;
o5 <= '0' after tphl when not to_bit(i5) = '0' else
'1' after tplh;
o6 <= '0' after tphl when not to_bit(i6) = '0' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX04-Test_vhd
-- ============================================================================
-- 74XX04 Hex Inverter (Test Bench)
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX04_TestBench is
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A74XX04_TestBench is
component A74XX04 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
i4 : in std_logic;
i5 : in std_logic;
i6 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic;
o5 : out std_logic;
o6 : out std_logic);
end component;
signal i : std_logic_vector (1 to 6);
signal o : std_logic_vector (1 to 6);
begin
i <= "UUUUUU",
"000000" after 10 ns,
"100000" after 20 ns,
"010000" after 30 ns,
"001000" after 40 ns,
"000100" after 50 ns,
"000010" after 60 ns,
"000001" after 70 ns,
"LLLLLL" after 80 ns,
"HLLLLL" after 90 ns,
"LHLLLL" after 100 ns,
"LLHLLL" after 110 ns,
"LLLHLL" after 120 ns,
"LLLLHL" after 130 ns,
"LLLLLH" after 140 ns;
gate: A74XX04
generic map (
tphl => 5 ns, tplh => 7 ns)
port map (
i(1), i(2), i(3), i(4), i(5), i(6),
o(1), o(2), o(3), o(4), o(5), o(6));
end architecture;
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VHDL PROGRAM OF A74XX08_vhd
-- ============================================================================
-- 74XX08 Quad 2-Input AND Gates
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX08 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
a4 : in std_logic;
b4 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX08 is
begin
o1 <= '0' after tphl when (a1 and b1) = '0' else
'1' after tplh;
o2 <= '0' after tphl when (a2 and b2) = '0' else
'1' after tplh;
o3 <= '0' after tphl when (a3 and b3) = '0' else
'1' after tplh;
o4 <= '0' after tphl when (a4 and b4) = '0' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX08-Test_vhd
-- ============================================================================
-- 74XX08 Quad 2-Input AND Gates (Test Bench)
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX08_TestBench is
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A74XX08_TestBench is
component A74XX08 is
generic (
tplh : time;
tphl : time);
port (
a1 : in std_logic;
b1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
a4 : in std_logic;
b4 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic);
end component;
signal ab : std_logic_vector (1 to 2);
signal wx : std_logic_vector (1 to 2);
signal o : std_logic_vector (1 to 4);
begin
-- Normal test pattern
ab <= "UU",
"00" after 10 ns,
"01" after 20 ns,
"10" after 30 ns,
"11" after 40 ns,
"LL" after 50 ns,
"LH" after 60 ns,
"HL" after 70 ns,
"HH" after 80 ns;
-- Inverted test pattern
wx <= "UU",
"11" after 10 ns,
"10" after 20 ns,
"01" after 30 ns,
"00" after 40 ns,
"HH" after 50 ns,
"HL" after 60 ns,
"LH" after 70 ns,
"LL" after 80 ns;
-- Connect the testbench to the component
nand2: A74XX08
generic map (
tplh => 5 ns, tphl => 7 ns)
port map (
ab(1), ab(2),
ab(1), wx(2),
wx(1), ab(2),
wx(1), wx(2),
o(1), o(2), o(3), o(4));
end architecture;
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VHDL PROGRAM OF A74XX10_vhd
-- ============================================================================
-- 74XX10 Triple 3-Input NAND Gates
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX10 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
c1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
c2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
c3 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX10 is
begin
o1 <= '0' after tphl when (a1 and b1 and c1) = '1' else
'1' after tplh;
o2 <= '0' after tphl when (a2 and b2 and c2) = '1' else
'1' after tplh;
o3 <= '0' after tphl when (a3 and b3 and c3) = '1' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX10-Test_vhd
-- ============================================================================
-- 74XX10 Triple 3-Input NAND Gates (Test Bench)
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX10_TestBench is
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A74XX10_TestBench is
component A74XX10 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
c1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
c2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
c3 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic);
end component;
signal abc : std_logic_vector (1 to 3);
signal xyz : std_logic_vector (1 to 3);
signal o : std_logic_vector (1 to 3);
begin
-- Normal test pattern
abc <= "UUU",
"000" after 10 ns,
"001" after 20 ns,
"010" after 30 ns,
"011" after 40 ns,
"100" after 50 ns,
"101" after 60 ns,
"110" after 70 ns,
"111" after 80 ns,
"LLL" after 90 ns,
"LLH" after 100 ns,
"LHL" after 110 ns,
"LHH" after 120 ns,
"HLL" after 130 ns,
"HLH" after 140 ns,
"HHL" after 150 ns,
"HHH" after 160 ns;
-- Inverted test pattern
xyz <= "UUU",
"111" after 10 ns,
"110" after 20 ns,
"101" after 30 ns,
"100" after 40 ns,
"011" after 50 ns,
"010" after 60 ns,
"001" after 70 ns,
"000" after 80 ns,
"HHH" after 90 ns,
"HHL" after 100 ns,
"HLH" after 110 ns,
"HLL" after 120 ns,
"LHH" after 130 ns,
"LHL" after 140 ns,
"LLH" after 150 ns,
"LLL" after 160 ns;
-- Connect the testbench to the component
gate: A74XX10
generic map (
tplh => 5 ns, tphl => 7 ns)
port map (
abc(1), abc(2), abc(3),
abc(1), xyz(2), abc(3),
xyz(1), xyz(2), xyz(3),
o(1), o(2), o(3));
end architecture;
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VHDL PROGRAM OF A74XX11_vhd
-- ============================================================================
-- 74XX11 Triple 3-Input AND Gates
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX11 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
c1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
c2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
c3 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX11 is
begin
o1 <= '0' after tphl when (a1 and b1 and c1) = '0' else
'1' after tplh;
o2 <= '0' after tphl when (a2 and b2 and c2) = '0' else
'1' after tplh;
o3 <= '0' after tphl when (a3 and b3 and c3) = '0' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX11-Test_vhd
-- ============================================================================
-- 74XX11 Triple 3-Input AND Gates (Test Bench)
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX11_TestBench is
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A74XX11_TestBench is
component A74XX11 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
c1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
c2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
c3 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic);
end component;
signal abc : std_logic_vector (1 to 3);
signal xyz : std_logic_vector (1 to 3);
signal o : std_logic_vector (1 to 3);
begin
-- Normal test pattern
abc <= "UUU",
"000" after 10 ns,
"001" after 20 ns,
"010" after 30 ns,
"011" after 40 ns,
"100" after 50 ns,
"101" after 60 ns,
"110" after 70 ns,
"111" after 80 ns,
"LLL" after 90 ns,
"LLH" after 100 ns,
"LHL" after 110 ns,
"LHH" after 120 ns,
"HLL" after 130 ns,
"HLH" after 140 ns,
"HHL" after 150 ns,
"HHH" after 160 ns;
-- Inverted test pattern
xyz <= "UUU",
"111" after 10 ns,
"110" after 20 ns,
"101" after 30 ns,
"100" after 40 ns,
"011" after 50 ns,
"010" after 60 ns,
"001" after 70 ns,
"000" after 80 ns,
"HHH" after 90 ns,
"HHL" after 100 ns,
"HLH" after 110 ns,
"HLL" after 120 ns,
"LHH" after 130 ns,
"LHL" after 140 ns,
"LLH" after 150 ns,
"LLL" after 160 ns;
-- Connect the testbench to the component
gate: A74XX11
generic map (
tplh => 5 ns, tphl => 7 ns)
port map (
abc(1), abc(2), abc(3),
abc(1), xyz(2), abc(3),
xyz(1), xyz(2), xyz(3),
o(1), o(2), o(3));
end architecture;
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VHDL PROGRAM OF A74XX21_vhd
-- ============================================================================
-- 74XX21 Dual 4-Input AND Gates
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX21 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
c1 : in std_logic;
d1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
c2 : in std_logic;
d2 : in std_logic;
o1 : out std_logic;
o2 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX21 is
begin
o1 <= '0' after tphl when (a1 and b1 and c1 and d1) = '0' else
'1' after tplh;
o2 <= '0' after tphl when (a2 and b2 and c2 and d2) = '0' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX27_vhd
-- ============================================================================
-- 74XX27 Triple 3-Input NOR Gates
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX27 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
c1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
c2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
c3 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX27 is
begin
o1 <= '0' after tphl when (a1 or b1 or c1) = '1' else
'1' after tplh;
o2 <= '0' after tphl when (a2 or b2 or c2) = '1' else
'1' after tplh;
o3 <= '0' after tphl when (a3 or b3 or c3) = '1' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX30_vhd
-- ============================================================================
-- 74XX30 8-Input NAND Gate
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX30 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
e : in std_logic;
f : in std_logic;
g : in std_logic;
h : in std_logic;
o : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX30 is
begin
o <= '0' after tphl when (a and b and c and d and e and f and g and h) = '1' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX32_vhd
-- ============================================================================
-- 74XX32 Quad 2-Input OR Gates
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX32 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
a4 : in std_logic;
b4 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX32 is
begin
o1 <= '0' after tphl when (a1 or b1) = '0' else
'1' after tplh;
o2 <= '0' after tphl when (a2 or b2) = '0' else
'1' after tplh;
o3 <= '0' after tphl when (a3 or b3) = '0' else
'1' after tplh;
o4 <= '0' after tphl when (a4 or b4) = '0' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX42_vhd
-- ============================================================================
-- 74XX42 BCD to Decimal Decoder (1-of-10)
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX42 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
o0_n : out std_logic;
o1_n : out std_logic;
o2_n : out std_logic;
o3_n : out std_logic;
o4_n : out std_logic;
o5_n : out std_logic;
o6_n : out std_logic;
o7_n : out std_logic;
o8_n : out std_logic;
o9_n : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A74XX42 is
signal a : std_logic_vector (3 downto 0);
begin
a <= not ((not a3) & (not a2) & (not a1) & (not a0));
o0_n <= '0' after tphl when (a = "0000") or (a = "LLLL") else
'1' after tplh;
o1_n <= '0' after tphl when (a = "0001") or (a = "LLLH")else
'1' after tplh;
o2_n <= '0' after tphl when (a = "0010") or (a = "LLHL")else
'1' after tplh;
o3_n <= '0' after tphl when (a = "0011") or (a = "LLHH")else
'1' after tplh;
o4_n <= '0' after tphl when (a = "0100") or (a = "LHLL")else
'1' after tplh;
o5_n <= '0' after tphl when (a = "0101") or (a = "LHLH")else
'1' after tplh;
o6_n <= '0' after tphl when (a = "0110") or (a = "LHHL")else
'1' after tplh;
o7_n <= '0' after tphl when (a = "0111") or (a = "LHHH")else
'1' after tplh;
o8_n <= '0' after tphl when (a = "1000") or (a = "HLLL")else
'1' after tplh;
o9_n <= '0' after tphl when (a = "1001") or (a = "HLLH")else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A74XX47_vhd
-- ============================================================================
-- 74XX47 BCD to 7-Segment Decoder/Driver
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX47 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
lt_n : in std_logic;
rbi_n : in std_logic;
rbo_n : inout std_logic;
a_n : out std_logic;
b_n : out std_logic;
c_n : out std_logic;
d_n : out std_logic;
e_n : out std_logic;
f_n : out std_logic;
g_n : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behaviour of A74XX47 is
begin
process (lt_n, rbi_n, rbo_n, a3, a2, a1, a0)
variable a : std_logic_vector (3 downto 0);
begin
-- I would rather write something more obvious like:
--
-- a := to_bit(a3) & to_bit(a2) & to_bit(a1) & to_bit(a0)
--
-- But VDHL won't accept it so I'm using logic operators to do the
-- to_bit conversion. They are optimised away during synthesis.
a := not ((not a3) & (not a2) & (not a1) & (not a0));
if (to_bit(rbo_n) = '0') then
-- Blanking input takes priority
a_n <= '1' after tplh;
b_n <= '1' after tplh;
c_n <= '1' after tplh;
d_n <= '1' after tplh;
e_n <= '1' after tplh;
f_n <= '1' after tplh;
g_n <= '1' after tplh;
elsif (to_bit(lt_n) = '0') then
-- Then a lamp test
a_n <= '0' after tphl;
b_n <= '0' after tphl;
c_n <= '0' after tphl;
d_n <= '0' after tphl;
e_n <= '0' after tphl;
f_n <= '0' after tphl;
g_n <= '0' after tphl;
rbo_n <= '1' after tplh;
elsif ((a = "0000") and (to_bit(rbi_n) = '0')) then
-- Suppressing a zero?
a_n <= '1' after tplh;
b_n <= '1' after tplh;
c_n <= '1' after tplh;
d_n <= '1' after tplh;
e_n <= '1' after tplh;
f_n <= '1' after tplh;
g_n <= '1' after tplh;
rbo_n <= '0' after tphl;
else
-- Normal digit display
case a is
when "0000" =>
a_n <= '0' after tphl;
b_n <= '0' after tphl;
c_n <= '0' after tphl;
d_n <= '0' after tphl;
e_n <= '0' after tphl;
f_n <= '0' after tphl;
g_n <= '1' after tplh;
when "0001" =>
a_n <= '1' after tplh;
b_n <= '0' after tphl;
c_n <= '0' after tphl;
d_n <= '1' after tplh;
e_n <= '1' after tplh;
f_n <= '1' after tplh;
g_n <= '1' after tplh;
when "0010" =>
a_n <= '0' after tphl;
b_n <= '0' after tphl;
c_n <= '1' after tplh;
d_n <= '0' after tphl;
e_n <= '0' after tphl;
f_n <= '1' after tplh;
g_n <= '0' after tphl;
when "0011" =>
a_n <= '0' after tphl;
b_n <= '0' after tphl;
c_n <= '0' after tphl;
d_n <= '0' after tphl;
e_n <= '1' after tplh;
f_n <= '1' after tplh;
g_n <= '0' after tphl;
when "0100" =>
a_n <= '1' after tplh;
b_n <= '0' after tphl;
c_n <= '0' after tphl;
d_n <= '1' after tplh;
e_n <= '1' after tplh;
f_n <= '0' after tphl;
g_n <= '0' after tphl;
when "0101" =>
a_n <= '0' after tphl;
b_n <= '1' after tplh;
c_n <= '0' after tphl;
d_n <= '0' after tphl;
e_n <= '1' after tplh;
f_n <= '0' after tphl;
g_n <= '0' after tphl;
when "0110" =>
a_n <= '1' after tplh;
b_n <= '1' after tplh;
c_n <= '0' after tphl;
d_n <= '0' after tphl;
e_n <= '0' after tphl;
f_n <= '0' after tphl;
g_n <= '0' after tphl;
when "0111" =>
a_n <= '0' after tphl;
b_n <= '0' after tphl;
c_n <= '0' after tphl;
d_n <= '1' after tplh;
e_n <= '1' after tplh;
f_n <= '1' after tplh;
g_n <= '1' after tplh;
when "1000" =>
a_n <= '0' after tphl;
b_n <= '0' after tphl;
c_n <= '0' after tphl;
d_n <= '0' after tphl;
e_n <= '0' after tphl;
f_n <= '0' after tphl;
g_n <= '0' after tphl;
when "1001" =>
a_n <= '0' after tphl;
b_n <= '0' after tphl;
c_n <= '0' after tphl;
d_n <= '1' after tplh;
e_n <= '1' after tplh;
f_n <= '0' after tphl;
g_n <= '0' after tphl;
when "1010" =>
a_n <= '1' after tplh;
b_n <= '1' after tplh;
c_n <= '1' after tplh;
d_n <= '0' after tphl;
e_n <= '0' after tphl;
f_n <= '1' after tplh;
g_n <= '0' after tphl;
when "1011" =>
a_n <= '1' after tplh;
b_n <= '1' after tplh;
c_n <= '0' after tphl;
d_n <= '0' after tphl;
e_n <= '1' after tplh;
f_n <= '1' after tplh;
g_n <= '0' after tphl;
when "1100" =>
a_n <= '1' after tplh;
b_n <= '0' after tphl;
c_n <= '1' after tplh;
d_n <= '1' after tplh;
e_n <= '1' after tplh;
f_n <= '0' after tphl;
g_n <= '0' after tphl;
when "1101" =>
a_n <= '0' after tphl;
b_n <= '1' after tplh;
c_n <= '1' after tplh;
d_n <= '0' after tphl;
e_n <= '1' after tplh;
f_n <= '0' after tphl;
g_n <= '0' after tphl;
when "1110" =>
a_n <= '1' after tplh;
b_n <= '1' after tplh;
c_n <= '1' after tplh;
d_n <= '0' after tphl;
e_n <= '0' after tphl;
f_n <= '0' after tphl;
g_n <= '0' after tphl;
when others =>
a_n <= '1' after tplh;
b_n <= '1' after tplh;
c_n <= '1' after tplh;
d_n <= '1' after tplh;
e_n <= '1' after tplh;
f_n <= '1' after tplh;
g_n <= '1' after tplh;
end case;
rbo_n <= '1' after tphl;
end if;
end process;
end architecture;
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VHDL PROGRAM OF A74XX126_vhd
-- ============================================================================
-- 74XX126 Quad Buffer/Line Driver (3-State)
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX126 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns;
tpzh : time := 0 ns;
tpzl : time := 0 ns;
tphz : time := 0 ns;
tplz : time := 0 ns);
port (
a1 : in std_logic;
oe1 : in std_logic;
a2 : in std_logic;
oe2 : in std_logic;
a3 : in std_logic;
oe3 : in std_logic;
a4 : in std_logic;
oe4 : in std_logic;
o1 : out std_ulogic;
o2 : out std_ulogic;
o3 : out std_ulogic;
o4 : out std_ulogic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A74XX126 is
signal v1 : std_logic := 'U';
signal v2 : std_logic := 'U';
signal v3 : std_logic := 'U';
signal v4 : std_logic := 'U';
signal c1 : std_logic := 'U';
signal c2 : std_logic := 'U';
signal c3 : std_logic := 'U';
signal c4 : std_logic := 'U';
begin
-- I have tried several different ways of including the propagation delays
-- in this model but I am yet to find a technique that will pass Xilinx
-- synthesis without reporting a 'bad synchronous description' error.
-- Copy inputs to local signals adding delay
v1 <= '0' after tphl when to_bit(a1) = '0' else
'1' after tplh;
v2 <= '0' after tphl when to_bit(a2) = '0' else
'1' after tplh;
v3 <= '0' after tphl when to_bit(a3) = '0' else
'1' after tplh;
v4 <= '0' after tphl when to_bit(a4) = '0' else
'1' after tplh;
-- Copy control inputs signal adding delay
c1 <= '0' after tplz when to_bit(oe1) = '0' and to_bit(a1) = '0' else
'0' after tphz when to_bit(oe1) = '0' and to_bit(a1) = '1' else
'1' after tpzl when to_bit(oe1) = '1' and to_bit(a1) = '0' else
'1' after tpzh when to_bit(oe1) = '1' and to_bit(a1) = '1';
c2 <= '0' after tplz when to_bit(oe2) = '0' and to_bit(a2) = '0' else
'0' after tphz when to_bit(oe2) = '0' and to_bit(a2) = '1' else
'1' after tpzl when to_bit(oe2) = '1' and to_bit(a2) = '0' else
'1' after tpzh when to_bit(oe2) = '1' and to_bit(a2) = '1';
c3 <= '0' after tplz when to_bit(oe3) = '0' and to_bit(a3) = '0' else
'0' after tphz when to_bit(oe3) = '0' and to_bit(a3) = '1' else
'1' after tpzl when to_bit(oe3) = '1' and to_bit(a3) = '0' else
'1' after tpzh when to_bit(oe3) = '1' and to_bit(a3) = '1';
c4 <= '0' after tplz when to_bit(oe4) = '0' and to_bit(a4) = '0' else
'0' after tphz when to_bit(oe4) = '0' and to_bit(a4) = '1' else
'1' after tpzl when to_bit(oe4) = '1' and to_bit(a4) = '0' else
'1' after tpzh when to_bit(oe4) = '1' and to_bit(a4) = '1';
-- Set the outputs
o1 <= v1 when to_bit(c1) = '1' else 'Z';
o2 <= v2 when to_bit(c2) = '1' else 'Z';
o3 <= v3 when to_bit(c3) = '1' else 'Z';
o4 <= v4 when to_bit(c4) = '1' else 'Z';
end architecture;
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VHDL PROGRAM OF A74XX151_vhd
-- ============================================================================
-- 74XX151 8-Input Multiplexer
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A74XX151 is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
en_n : in std_logic;
s0 : in std_logic;
s1 : in std_logic;
s2 : in std_logic;
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
i4 : in std_logic;
i5 : in std_logic;
i6 : in std_logic;
i7 : in std_logic;
o : out std_logic;
o_n : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A74XX151 is
signal value : std_logic := 'U';
begin
-- Process changes to the select or input lines
process (s0, s1, s2, i0, i1, i2, i3, i4, i5, i6, i7)
variable sel : std_logic_vector (0 to 2);
begin
sel := not((not s2) & (not s1) & (not s0));
case sel is
when "000" => value <= i0;
when "001" => value <= i1;
when "010" => value <= i2;
when "011" => value <= i3;
when "100" => value <= i4;
when "101" => value <= i5;
when "110" => value <= i6;
when others => value <= i7;
end case;
end process;
-- Set the actual outputs (NB. Same timing for both o and o_n)
o <= '0' after tphl when ((not en_n) and value) = '0' else
'1' after tplh;
o_n <= '1' after tphl when ((not en_n) and value) = '0' else
'0' after tplh;
end architecture;
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VHDL PROGRAM OF A4050B_vhd
-- ============================================================================
-- 4050B Hex Non-Inverting Buffers
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A4050B is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
i4 : in std_logic;
i5 : in std_logic;
i6 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic;
o5 : out std_logic;
o6 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A4050B is
begin
o1 <= '1' after tplh when to_bit(i1) = '1' else
'0' after tphl;
o2 <= '1' after tplh when to_bit(i2) = '1' else
'0' after tphl;
o3 <= '1' after tplh when to_bit(i3) = '1' else
'0' after tphl;
o4 <= '1' after tplh when to_bit(i4) = '1' else
'0' after tphl;
o5 <= '1' after tplh when to_bit(i5) = '1' else
'0' after tphl;
o6 <= '1' after tplh when to_bit(i6) = '1' else
'0' after tphl;
end architecture;
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VHDL PROGRAM OF A4049B_vhd
-- ============================================================================
-- 4049B Hex Inverting Buffers
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A4049B is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
i4 : in std_logic;
i5 : in std_logic;
i6 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic;
o5 : out std_logic;
o6 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A4049B is
begin
o1 <= '1' after tplh when to_bit(i1) = '0' else
'0' after tphl;
o2 <= '1' after tplh when to_bit(i2) = '0' else
'0' after tphl;
o3 <= '1' after tplh when to_bit(i3) = '0' else
'0' after tphl;
o4 <= '1' after tplh when to_bit(i4) = '0' else
'0' after tphl;
o5 <= '1' after tplh when to_bit(i5) = '0' else
'0' after tphl;
o6 <= '1' after tplh when to_bit(i6) = '0' else
'0' after tphl;
end architecture;
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VHDL PROGRAM OF A4041B_vhd
-- ============================================================================
-- 4041B Quadruple True/Complement Buffer
--
-- Copyright (C),2005 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A4041B is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
i4 : in std_logic;
o1 : out std_logic;
o1_n : out std_logic;
o2 : out std_logic;
o2_n : out std_logic;
o3 : out std_logic;
o3_n : out std_logic;
o4 : out std_logic;
o4_n : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A4041B is
begin
o1 <= '1' after tplh when to_bit(i1) = '1' else
'0' after tphl;
o1_n <= '1' after tplh when to_bit(i1) = '0' else
'0' after tphl;
o2 <= '1' after tplh when to_bit(i2) = '1' else
'0' after tphl;
o2_n <= '1' after tplh when to_bit(i2) = '0' else
'0' after tphl;
o3 <= '1' after tplh when to_bit(i3) = '1' else
'0' after tphl;
o3_n <= '1' after tplh when to_bit(i3) = '0' else
'0' after tphl;
o4 <= '1' after tplh when to_bit(i4) = '1' else
'0' after tphl;
o4_n <= '1' after tplh when to_bit(i4) = '0' else
'0' after tphl;
end architecture;
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VHDL PROGRAM OF A4040B_vhd
-- ============================================================================
-- 4030B 12-Stage Binary Counter
--
-- Copyright (C),2005 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A4040B is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
cp_n : in std_logic;
mr : in std_logic;
o0 : out std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic;
o5 : out std_logic;
o6 : out std_logic;
o7 : out std_logic;
o8 : out std_logic;
o9 : out std_logic;
o10 : out std_logic;
o11 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A4040B is
-- Internal flip-flop states
signal ff0 : std_logic := 'U';
signal ff1 : std_logic := 'U';
signal ff2 : std_logic := 'U';
signal ff3 : std_logic := 'U';
signal ff4 : std_logic := 'U';
signal ff5 : std_logic := 'U';
signal ff6 : std_logic := 'U';
signal ff7 : std_logic := 'U';
signal ff8 : std_logic := 'U';
signal ff9 : std_logic := 'U';
signal ffa : std_logic := 'U';
signal ffb : std_logic := 'U';
begin
-- Handle async. reset and active low clock pulse
process (cp_n, mr)
begin
if (to_bit(mr) = '1') then
ff0 <= '0';
ff1 <= '0';
ff2 <= '0';
ff3 <= '0';
ff4 <= '0';
ff5 <= '0';
ff6 <= '0';
ff7 <= '0';
ff8 <= '0';
ff9 <= '0';
ffa <= '0';
ffb <= '0';
elsif falling_edge(cp_n) then
ff0 <= not ff0;
if ff0 = '1' then
ff1 <= not ff1;
end if;
if ff1 = '1' then
ff2 <= not ff2;
end if;
if ff2 = '1' then
ff3 <= not ff3;
end if;
if ff3 = '1' then
ff4 <= not ff4;
end if;
if ff4 = '1' then
ff5 <= not ff5;
end if;
if ff5 = '1' then
ff6 <= not ff6;
end if;
if ff6 = '1' then
ff7 <= not ff7;
end if;
if ff7 = '1' then
ff8 <= not ff8;
end if;
if ff8 = '1' then
ff9 <= not ff9;
end if;
if ff9 = '1' then
ffa <= not ffa;
end if;
if ffa = '1' then
ffb <= not ffb;
end if;
end if;
end process;
-- Copy flip-flop states to output adding delay
o0 <= '1' after tplh when to_bit(ff0) = '1' else
'0' after tphl;
o1 <= '1' after tplh when to_bit(ff1) = '1' else
'0' after tphl;
o2 <= '1' after tplh when to_bit(ff2) = '1' else
'0' after tphl;
o3 <= '1' after tplh when to_bit(ff3) = '1' else
'0' after tphl;
o4 <= '1' after tplh when to_bit(ff4) = '1' else
'0' after tphl;
o5 <= '1' after tplh when to_bit(ff5) = '1' else
'0' after tphl;
o6 <= '1' after tplh when to_bit(ff6) = '1' else
'0' after tphl;
o7 <= '1' after tplh when to_bit(ff7) = '1' else
'0' after tphl;
o8 <= '1' after tplh when to_bit(ff8) = '1' else
'0' after tphl;
o9 <= '1' after tplh when to_bit(ff9) = '1' else
'0' after tphl;
o10 <= '1' after tplh when to_bit(ffa) = '1' else
'0' after tphl;
o11 <= '1' after tplh when to_bit(ffb) = '1' else
'0' after tphl;
end architecture;
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VHDL PROGRAM OF A4040B_vhd
-- ============================================================================
-- 4030B 12-Stage Binary Counter
--
-- Copyright (C),2005 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A4040B is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
cp_n : in std_logic;
mr : in std_logic;
o0 : out std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic;
o5 : out std_logic;
o6 : out std_logic;
o7 : out std_logic;
o8 : out std_logic;
o9 : out std_logic;
o10 : out std_logic;
o11 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A4040B is
-- Internal flip-flop states
signal ff0 : std_logic := 'U';
signal ff1 : std_logic := 'U';
signal ff2 : std_logic := 'U';
signal ff3 : std_logic := 'U';
signal ff4 : std_logic := 'U';
signal ff5 : std_logic := 'U';
signal ff6 : std_logic := 'U';
signal ff7 : std_logic := 'U';
signal ff8 : std_logic := 'U';
signal ff9 : std_logic := 'U';
signal ffa : std_logic := 'U';
signal ffb : std_logic := 'U';
begin
-- Handle async. reset and active low clock pulse
process (cp_n, mr)
begin
if (to_bit(mr) = '1') then
ff0 <= '0';
ff1 <= '0';
ff2 <= '0';
ff3 <= '0';
ff4 <= '0';
ff5 <= '0';
ff6 <= '0';
ff7 <= '0';
ff8 <= '0';
ff9 <= '0';
ffa <= '0';
ffb <= '0';
elsif falling_edge(cp_n) then
ff0 <= not ff0;
if ff0 = '1' then
ff1 <= not ff1;
end if;
if ff1 = '1' then
ff2 <= not ff2;
end if;
if ff2 = '1' then
ff3 <= not ff3;
end if;
if ff3 = '1' then
ff4 <= not ff4;
end if;
if ff4 = '1' then
ff5 <= not ff5;
end if;
if ff5 = '1' then
ff6 <= not ff6;
end if;
if ff6 = '1' then
ff7 <= not ff7;
end if;
if ff7 = '1' then
ff8 <= not ff8;
end if;
if ff8 = '1' then
ff9 <= not ff9;
end if;
if ff9 = '1' then
ffa <= not ffa;
end if;
if ffa = '1' then
ffb <= not ffb;
end if;
end if;
end process;
-- Copy flip-flop states to output adding delay
o0 <= '1' after tplh when to_bit(ff0) = '1' else
'0' after tphl;
o1 <= '1' after tplh when to_bit(ff1) = '1' else
'0' after tphl;
o2 <= '1' after tplh when to_bit(ff2) = '1' else
'0' after tphl;
o3 <= '1' after tplh when to_bit(ff3) = '1' else
'0' after tphl;
o4 <= '1' after tplh when to_bit(ff4) = '1' else
'0' after tphl;
o5 <= '1' after tplh when to_bit(ff5) = '1' else
'0' after tphl;
o6 <= '1' after tplh when to_bit(ff6) = '1' else
'0' after tphl;
o7 <= '1' after tplh when to_bit(ff7) = '1' else
'0' after tphl;
o8 <= '1' after tplh when to_bit(ff8) = '1' else
'0' after tphl;
o9 <= '1' after tplh when to_bit(ff9) = '1' else
'0' after tphl;
o10 <= '1' after tplh when to_bit(ffa) = '1' else
'0' after tphl;
o11 <= '1' after tplh when to_bit(ffb) = '1' else
'0' after tphl;
end architecture;
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VHDL PROGRAM OF A4030B_vhd
-- ============================================================================
-- 4030B Quad 2-Input Exclusive-OR Gates
--
-- Copyright (C),2005 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A4030B is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a1 : in std_logic;
b1 : in std_logic;
a2 : in std_logic;
b2 : in std_logic;
a3 : in std_logic;
b3 : in std_logic;
a4 : in std_logic;
b4 : in std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A4030B is
begin
o1 <= '1' after tplh when (a1 xor b1) = '1' else
'0' after tphl;
o2 <= '1' after tplh when (a2 xor b2) = '1' else
'0' after tphl;
o3 <= '1' after tplh when (a3 xor b3) = '1' else
'0' after tphl;
o4 <= '1' after tplh when (a4 xor b4) = '1' else
'0' after tphl;
end architecture;
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VHDL PROGRAM OF A4029B_vhd
-- ============================================================================
-- 4029B Synchronous Up/Down Counter, Binary/Decade Counter
--
-- Copyright (C),2005 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A4029B is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
cp : in std_logic;
pl : in std_logic;
ce_n : in std_logic;
bin : in std_logic;
up : in std_logic;
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
o0 : out std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
tc_n : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture behaviour of A4029B is
signal clk : std_logic := 'U';
signal dn : std_logic := 'U';
signal dec : std_logic := 'U';
signal is_0 : std_logic := 'U';
signal is_9 : std_logic := 'U';
signal is_f : std_logic := 'U';
signal data : std_logic_vector (3 downto 0) := "UUUU";
begin
dn <= not up;
dec <= not bin;
-- Combine inputs that trigger change
clk <= cp and (not pl) and (not ce_n);
-- Handle asynchronous parallel load
process (pl)
begin
if rising_edge(pl) then
data(0) <= not (not i0);
data(1) <= not (not i1);
data(2) <= not (not i2);
data(3) <= not (not i3);
end if;
end process;
-- Process clock pulses
process (clk)
begin
if rising_edge(clk) then
if to_bit(up) = '1' then
if to_bit(bin) = '1' then
-- Binary Increment
case data is
when "0000" => data <= "0001";
when "0001" => data <= "0010";
when "0010" => data <= "0011";
when "0011" => data <= "0100";
when "0100" => data <= "0101";
when "0101" => data <= "0110";
when "0110" => data <= "0111";
when "0111" => data <= "1000";
when "1000" => data <= "1001";
when "1001" => data <= "1010";
when "1010" => data <= "1011";
when "1011" => data <= "1100";
when "1100" => data <= "1101";
when "1101" => data <= "1110";
when "1110" => data <= "1111";
when others => data <= "0000";
end case;
else
-- Decade Increment
case data is
when "0000" => data <= "0001";
when "0001" => data <= "0010";
when "0010" => data <= "0011";
when "0011" => data <= "0100";
when "0100" => data <= "0101";
when "0101" => data <= "0110";
when "0110" => data <= "0111";
when "0111" => data <= "1000";
when "1000" => data <= "1001";
when "1001" => data <= "0000";
when "1010" => data <= "1011";
when "1011" => data <= "0110";
when "1100" => data <= "1101";
when "1101" => data <= "0100";
when "1110" => data <= "1111";
when others => data <= "0010";
end case;
end if;
else
if to_bit(bin) = '1' then
-- Binary Decrement
case data is
when "0000" => data <= "1111";
when "0001" => data <= "0000";
when "0010" => data <= "0001";
when "0011" => data <= "0010";
when "0100" => data <= "0011";
when "0101" => data <= "0100";
when "0110" => data <= "0101";
when "0111" => data <= "0110";
when "1000" => data <= "0111";
when "1001" => data <= "1000";
when "1010" => data <= "1001";
when "1011" => data <= "1010";
when "1100" => data <= "1011";
when "1101" => data <= "1100";
when "1110" => data <= "1101";
when others => data <= "1110";
end case;
else
-- Decade Decrement
case data is
when "0000" => data <= "1001";
when "0001" => data <= "0000";
when "0010" => data <= "0001";
when "0011" => data <= "0010";
when "0100" => data <= "0011";
when "0101" => data <= "0100";
when "0110" => data <= "0101";
when "0111" => data <= "0110";
when "1000" => data <= "0111";
when "1001" => data <= "1000";
when "1010" => data <= "1001";
when "1011" => data <= "1010";
when "1100" => data <= "1011";
when "1101" => data <= "1100";
when "1110" => data <= "1101";
when others => data <= "1110";
end case;
end if;
end if;
end if;
end process;
-- Copy internal state to outputs adding delays
o0 <= '1' after tplh when to_bit(data(0)) = '1' else
'0' after tphl;
o1 <= '1' after tplh when to_bit(data(1)) = '1' else
'0' after tphl;
o2 <= '1' after tplh when to_bit(data(2)) = '1' else
'0' after tphl;
o3 <= '1' after tplh when to_bit(data(3)) = '1' else
'0' after tphl;
-- Set the terminal count output
is_0 <= not data(0) and not data(1) and not data(2) and not data(3);
is_9 <= data(0) and data(3);
is_f <= data(0) and data(1) and data(2) and data(3);
tc_n <= '0' after tphl when (not ce_n and (
(dn and is_0) or
(bin and up and is_f) or
(dec and up and is_9))) = '1' else
'1' after tplh;
end architecture;
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VHDL PROGRAM OF A4028B_vhd
-- ============================================================================
-- 4028B 1-of-10 Decoder
--
-- Copyright (C),2005 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A4028B is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
o0 : out std_logic;
o1 : out std_logic;
o2 : out std_logic;
o3 : out std_logic;
o4 : out std_logic;
o5 : out std_logic;
o6 : out std_logic;
o7 : out std_logic;
o8 : out std_logic;
o9 : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
architecture dataflow of A4028B is
signal n0 : std_logic := 'U';
signal n1 : std_logic := 'U';
signal n2 : std_logic := 'U';
signal n3 : std_logic := 'U';
begin
-- Create negated inputs for use in outputs
n0 <= not a0;
n1 <= not a1;
n2 <= not a2;
n3 <= not a3;
-- Create outputs adding delays
o0 <= '1' after tplh when (n3 and n2 and n1 and n0) = '1' else
'0' after tphl;
o1 <= '1' after tplh when (n3 and n2 and n1 and a0) = '1' else
'0' after tphl;
o2 <= '1' after tplh when (n3 and n2 and a1 and n0) = '1' else
'0' after tphl;
o3 <= '1' after tplh when (n3 and n2 and a1 and a0) = '1' else
'0' after tphl;
o4 <= '1' after tplh when (n3 and a2 and n1 and n0) = '1' else
'0' after tphl;
o5 <= '1' after tplh when (n3 and a2 and n1 and a0) = '1' else
'0' after tphl;
o6 <= '1' after tplh when (n3 and a2 and a1 and n0) = '1' else
'0' after tphl;
o7 <= '1' after tplh when (n3 and a2 and a1 and a0) = '1' else
'0' after tphl;
o8 <= '1' after tplh when (a3 and n2 and n1 and n0) = '1' else
'0' after tphl;
o9 <= '1' after tplh when (a3 and n2 and n1 and a0) = '1' else
'0' after tphl;
end architecture;
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VHDL PROGRAM OF A4027B_vhd
-- ============================================================================
-- 4027B Dual JK Flip Flop
--
-- Copyright (C),2004 Andrew John Jacobs.
--
-- This program is provided free of charge for educational purposes
--
-- Redistribution and use in binary form without modification, is permitted
-- provided that the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided
-- with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity A4027B is
generic (
tplh : time := 0 ns;
tphl : time := 0 ns);
port (
s1 : in std_logic; -- Set
c1 : in std_logic; -- Clear
j1 : in std_logic; -- Data
k1 : in std_logic; -- Data
cp1 : in std_logic; -- Clock
s2 : in std_logic;
c2 : in std_logic;
j2 : in std_logic;
k2 : in std_logic;
cp2 : in std_logic;
o1 : out std_logic; -- Output
o1_n : out std_logic; -- Output inverted (usually)
o2 : out std_logic;
o2_n : out std_logic);
end entity;
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
library work;
architecture behaviour of A4027B is
-- Internal flip flop states
signal ff1 : std_logic_vector (1 to 2);
signal ff2 : std_logic_vector (1 to 2);
begin
-- Flip flop 1
process (cp1,s1,c1)
variable jk : std_logic_vector (1 to 2);
begin
if ((s1 or c1) = '1') then
ff1(1) <= not (not s1);
ff1(2) <= not (not c1);
elsif rising_edge(cp1) then
jk := not ((not j1) & (not k1));
case jk is
when "10" => ff1 <= "10";
when "01" => ff1 <= "01";
when "11" => ff1 <= not(ff1(1)) & not(ff1(2));
when others =>
end case;
end if;
end process;
-- Flip flop 2
process (cp2,s2,c2)
variable jk : std_logic_vector (1 to 2);
begin
if ((s2 or c2) = '1') then
ff2(1) <= not (not s2);
ff2(2) <= not (not c2);
elsif rising_edge(cp2) then
jk := not ((not j2) & (not k2));
case jk is
when "10" => ff2 <= "10";
when "01" => ff2 <= "01";
when "11" => ff2 <= not(ff2(1)) & not(ff2(2));
when others =>
end case;
end if;
end process;
-- Copy state to outputs adding propagation delay
o1 <= '1' after tplh when to_bit(ff1(1)) = '1' else
'0' after tphl;
o1_n <= '1' after tplh when to_bit(ff1(2)) = '1' else
'0' after tphl;
o2 <= '1' after tplh when to_bit(ff2(1)) = '1' else
'0' after tphl;
o2_n <= '1' after tplh when to_bit(ff2(2)) = '1' else
'0' after tphl;
end architecture;
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